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1/20 may 2000 m24c16, m24c08 m24c04, m24c02, m24c01 16/8/4/2/1 kbit serial i2c bus eeprom n two wire i 2 c serial interface supports 400 khz protocol n single supply voltage: C 4.5v to 5.5v for m24cxx C 2.5v to 5.5v for m24cxx-w C 1.8v to 3.6v for m24cxx-r n hardware write control n byte and page write (up to 16 bytes) n random and sequential read modes n self-timed programming cycle n automatic address incrementing n enhanced esd/latch-up behavior n 1 million erase/write cycles (minimum) n 40 year data retention (minimum) description these i 2 c-compatible electrically erasable programmable memory (eeprom) devices are organized as 2048/1024/512/256/128 x 8 bit (m24c16, m24c08, m24c04, m24c02, m24c01), and operate with a power supply down to 2.5 v (for the -w version of each device), and down to 1.8 v (for the -r version of each device). the m24c16, m24c08, m24c04, m24c02, m24c01 are available in plastic dual-in-line, plastic small outline and thin shrink small outline packages. the m24c16-r is also available in a chip-scale (sbga) package. figure 1. logic diagram ai02033 3 e0-e2 sda v cc m24cxx wc scl v ss table 1. signal names e0, e1, e2 chip enable inputs sda serial data/address input/ output scl serial clock wc write control v cc supply voltage v ss ground psdip8 (bn) 0.25 mm frame so8 (mn) 150 mil width tssop8 (dw) 169 mil width 8 1 8 1 8 1 sbga sbga5 (ea) 75 mil width
m24c16, m24c08, m24c04, m24c02, m24c01 2/20 figure 2a. dip connections note: 1. nc = not connected figure 2b. so connections note: 1. nc = not connected figure 2c. standard-tssop connections note: 1. nc = not connected sda v ss scl wc v cc / e2 ai02034d m24cxx 1 2 3 4 8 7 6 5 / e2 / e2 / e2 nc / e1 / e1 / e1 / nc nc / e0 / e0 / nc / nc nc /1kb /2kb /4kb /8kb 16kb 1 ai02035d 2 3 4 8 7 6 5 sda v ss scl wc v cc / e2 m24cxx / e2 / e2 / e2 nc / e1 / e1 / e1 / nc nc / e0 / e0 / nc / nc nc /1kb /2kb /4kb /8kb 16kb 1 ai02036d 2 3 4 8 7 6 5 sda v ss scl wc v cc / e2 m24cxx / e2 / e2 / e2 nc / e1 / e1 / e1 / nc nc / e0 / e0 / nc / nc nc /1kb /2kb /4kb /8kb 16kb figure 2d. sbga connections (top view, marking side, with balls on the underside) ai02796e scl v ss sda wc v cc m24c16 ball "1"
3/20 m24c16, m24c08, m24c04, m24c02, m24c01 these memory devices are compatible with the i 2 c memory standard. this is a two wire serial interface that uses a bi-directional data bus and serial clock. the memory carries a built-in 4-bit unique device type identifier code (1010) in accordance with the i 2 c bus definition. the memory behaves as a slave device in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and rw bit (as described in table 3), terminated by an acknowledge bit. when writing data to the memory, the memory inserts an acknowledge bit during the 9 th bit time, following the bus masters 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. power on reset: v cc lock-out write protect in order to prevent data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the internal reset is held active until the v cc voltage has reached the por threshold value, and all operations are figure 3. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus ai01665 v cc c bus sda r l master r l scl c bus 100 0 4 8 12 16 20 c bus (pf) maximum rp value (k w ) 10 1000 fc = 400khz fc = 100khz table 2. absolute maximum ratings 1 note: 1. except for the rating operating temperature range, stresses above those listed in the table absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditio ns above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the st sure program and other relevant quality document s. 2. mil-std-883c, 3015.7 (100 pf, 1500 w ) symbol parameter value unit t a ambient operating temperature -40 to 125 c t stg storage temperature -65 to 150 c t lead lead temperature during soldering psdip8: 10 sec so8: 40 sec tssop8: 40 sec sbga5: t.b.c. 260 215 215 t.b.c. c v io input or output range -0.6 to 6.5 v v cc supply voltage -0.3 to 6.5 v v esd electrostatic discharge voltage (human body model 2 ) 4000 v
m24c16, m24c08, m24c04, m24c02, m24c01 4/20 disabled C the device will not respond to any command. in the same way, when v cc drops from the operating voltage, below the por threshold value, all operations are disabled and the device will not respond to any command. a stable and valid v cc must be applied before applying any logic signal. signal description serial clock (scl) the scl input pin is used to strobe all data in and out of the memory. in applications where this line is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from the scl line to v cc . (figure 3 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of synchronization is not employed, and so the pull- up resistor is not necessary, provided that the master has a push-pull (rather than open drain) output. serial data (sda) the sda pin is bi-directional, and is used to transfer data in or out of the memory. it is an open drain output that may be wire-ored with other open drain or open collector signals on the bus. a pull up resistor must be connected from the sda bus to v cc . (figure 3 indicates how the value of the pull-up resistor can be calculated). chip enable (e2, e1, e0) these chip enable inputs are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (but see the description of memory addressing, on page 6, for more details). these inputs may be driven dynamically or tied to v cc or v ss to establish the device select code (but note that the v il and v ih levels for the inputs are cmos compatible, not ttl compatible). figure 4. i 2 c bus protocol scl sda scl sda sda start condition sda input sda change ai00792 stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
5/20 m24c16, m24c08, m24c04, m24c02, m24c01 write control (wc ) the hardware write control pin (wc ) is useful for protecting the entire contents of the memory from inadvertent erase/write. the write control signal is used to enable (wc =v il ) or disable (wc =v ih ) write instructions to the entire memory area. when unconnected, the wc input is internally read as v il , and write operations are allowed. when wc =1, device select and address bytes are acknowledged, data bytes are not acknowledged. please see the application note an404 for a more detailed description of the write control feature. device operation the memory device supports the i 2 c protocol. this is summarized in figure 4, and is compared with other serial bus protocols in application note an1001 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the master, and the other as the slave. a data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. the memory device is always a slave device in all communication. start condition start is identified by a high to low transition of the sda line while the clock, scl, is stable in the high state. a start condition must precede any data transfer command. the memory device continuously monitors (except during a programming cycle) the sda and scl lines for a start condition, and will not respond unless one is given. stop condition stop is identified by a low to high transition of the sda line while the clock scl is stable in the high state. a stop condition terminates communication between the memory device and the bus master. a stop condition at the end of a read command, after (and only after) a noack, forces the memory device into its standby state. a stop condition at the end of a write command triggers the internal eeprom write cycle. acknowledge bit (ack) an acknowledge signal is used to indicate a successful byte transfer. the bus transmitter, whether it be master or slave, releases the sda bus after sending eight bits of data. during the 9 th table 3. device select code 1 note: 1. the most significant bit, b7, is sent first. 2. e0, e1 and e2 are compared against the respective external pins on the memory device. 3. a10, a9 and a8 represent high significant bits of the address. device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 m24c01 select code 1010e2e1e0rw m24c02 select code 1010e2e1e0rw m24c04 select code 1010e2e1a8rw m24c08 select code 1010e2a9a8rw m24c16 select code 1010a10a9a8rw table 4. operating modes note: 1. x = v ih or v il . mode rw bit wc 1 bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 3 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 16 start, device select, rw = 0
m24c16, m24c08, m24c04, m24c02, m24c01 6/20 figure 5. write mode sequences with wc =1 (data write inhibited) stop start byte write dev sel byte addr data in wc start page write dev sel byte addr data in 1 data in 2 wc data in 3 ai02803b page write (cont'd) wc (cont'd) stop data in n ack ack no ack r/w ack ack no ack no ack r/w no ack no ack clock pulse period, the receiver pulls the sda bus low to acknowledge the receipt of the eight data bits. data input during data input, the memory device samples the sda bus signal on the rising edge of the clock, scl. for correct device operation, the sda signal must be stable during the clock low-to-high transition, and the data must change only when the scl line is low. memory addressing to start communication between the bus master and the slave memory, the master must initiate a start condition. following this, the master sends the 8-bit byte, shown in table 3, on the sda bus line (most significant bit first). this consists of the 7-bit device select code, and the 1-bit read/write designator (rw ). the device select code is further subdivided into: a 4-bit device type identifier, and a 3-bit chip enable address (e2, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on its chip enable inputs. when the device select code is received, the memory only responds if the chip enable code (shown in table 3) is the same as the pattern applied to its chip enable pins. those devices with larger memory capacities (the m24c16, m24c08 and m24c04) need more address bits. e0 is not available for use on devices that need to use address line a8; e1 is not available for devices that need to use address line a9, and e2 is not available for devices that need to use address line a10 (see figure 2a to figure 2d and table 3 for details). using the e0, e1 and e2 inputs pins, up to eight m24c02 (or m24c01), four m24c04, two m24c08 or one m24c16 device can be connected to one i 2 c bus. in each case, and in the hybrid cases, this gives a total memory
7/20 m24c16, m24c08, m24c04, m24c02, m24c01 figure 6. write mode sequences with wc =0 (data write enabled) stop start byte write dev sel byte addr data in wc start page write dev sel byte addr data in 1 data in 2 wc data in 3 ai02804 page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack r/w ack ack capacity of 16 kbits, 2 kbytes (except where m24c01 devices are used). the 8 th bit is the rw bit. this is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding memory gives an acknowledgment on the sda bus during the 9 th bit time. if the memory does not match the device select code, it deselects itself from the bus, and goes into stand-by mode. there are two modes both for read and write. these are summarized in table 4 and described later. a communication between the master and the slave is ended with a stop condition. write operations following a start condition the master sends a device select code with the rw bit set to 0, as shown in table 4. the memory acknowledges this, and waits for an address byte. the memory responds to the address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if the wc input pin is taken high. any write command with wc =1 (during a period of time from the start condition until the end of the address byte) will not modify the memory contents, and the accompanying data bytes will not be acknowledged (as shown in figure 5). byte write in the byte write mode, after the device select code and the address, the master sends one data byte. if the addressed location is write protected by the wc pin, the memory replies with a noack, and the location is not modified. if, instead, the wc pin has been held at 0, as shown in figure 6, the memory replies with an ack. the master terminates the transfer by generating a stop condition. page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they
m24c16, m24c08, m24c04, m24c02, m24c01 8/20 a stop condition at any other time does not trigger the internal write cycle. during the internal write cycle, the sda input is disabled internally, and the device does not respond to any requests. minimizing system delays by polling on ack during the internal write cycle, the memory disconnects itself from the bus, and copies the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in table 6b, but the typical time is shorter. to make use of this, an ack polling sequence can be used by the master. are all located in the same row in the memory: that is the most significant memory address bits are the same. if more bytes are sent than will fit up to the end of the row, a condition known as roll- over occurs. data starts to become overwritten, or otherwise altered. the master sends from one up to 16 bytes of data, each of which is acknowledged by the memory if the wc pin is low. if the wc pin is high, the contents of the addressed memory location are not modified, and each data byte is followed by a noack. after each byte is transferred, the internal byte address counter (the 4 least significant bits only) is incremented. the transfer is terminated by the master generating a stop condition. when the master generates a stop condition immediately after the ack bit (in the 10 th bit time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. figure 7. write cycle polling flowchart using ack write cycle in progress ai01847 next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop proceed write operation proceed random address read operation send byte address first byte of instruction with rw = 0 already decoded by m24xxx
9/20 m24c16, m24c08, m24c04, m24c02, m24c01 read operations read operations are performed independently of the state of the wc pin. random address read a dummy write is performed to load the address into the address counter, as shown in figure 8. then, without sending a stop condition, the master sends another start condition, and repeats the device select code, with the rw bit set to 1. the memory acknowledges this, and outputs the contents of the addressed byte. the master must not acknowledge the byte output, and terminates the transfer with a stop condition. the sequence, as shown in figure 7, is: C initial condition: a write is in progress. C step 1: the master issues a start condition followed by a device select code (the first byte of the new instruction). C step 2: if the memory is busy with the internal write cycle, no ack will be returned and the master goes back to step 1. if the memory has terminated the internal write cycle, it responds with an ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during step 1). figure 8. read mode sequences note: 1. the seven most significant bits of the device select code of a random read (in the 1 st and 3 rd bytes) must be identical. start dev sel * byte addr start dev sel data out 1 ai01942 data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack
m24c16, m24c08, m24c04, m24c02, m24c01 10/20 table 5a. dc characteristics (t a = 0 to 70 c, or C40 to 85 c; v cc = 4.5 to 5.5 v or 2.5 to 5.5 v) (t a = 0 to 70 c, or C40 to 85 c; v cc = 1.8 to 3.6 v) note: 1. this is preliminary data. symbol parameter test condition min. max. unit i li input leakage current (scl, sda) 0v v in v cc 2 a i lo output leakage current 0 v v out v cc, sda in hi-z 2 a i cc supply current v cc =5v, f c =400khz (rise/fall time < 30ns) 2ma -w series: v cc =2.5v, f c =400khz (rise/fall time < 30ns) 1ma -r series: v cc =1.8v, f c =400khz (rise/fall time < 30ns) 0.8 1 ma i cc1 supply current (stand-by) v in = v ss or v cc , v cc = 5 v 1 a -w series: v in = v ss or v cc , v cc = 2.5 v 0.5 a -r series: v in = v ss or v cc , v cc = 1.8 v 0.1 1 a v il input low voltage (e0, e1, e2, scl, sda) C 0.3 0.3 v cc v v ih input high voltage (e0, e1, e2, scl, sda) 0.7v cc v cc +1 v v il input low voltage (wc ) C 0.3 0.5 v v ih input high voltage (wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 3 ma, v cc = 5 v 0.4 v -w series: i ol = 2.1 ma, v cc = 2.5 v 0.4 v -r series: i ol = 0.7 ma, v cc = 1.8 v 0.2 1 v current address read the device has an internal address counter which is incremented each time a byte is read. for the current address read mode, following a start condition, the master sends a device select code with the rw bit set to 1. the memory acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the master terminates the transfer with a stop condition, as shown in figure 8, without acknowledging the byte output. sequential read this mode can be initiated with either a current address read or a random address read. the master does acknowledge the data byte output in this case, and the memory continues to output the next byte in sequence. to terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a stop condition. the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter rolls-over and the memory continues to output data from memory address 00h. acknowledge in read mode in all read modes, the memory waits, after each byte read, for an acknowledgment during the 9 th bit time. if the master does not pull the sda line low during this time, the memory terminates the data transfer and switches to its stand-by state.
11/20 m24c16, m24c08, m24c04, m24c02, m24c01 table 5b. dc characteristics 1 (t a = C40 to 125 c; v cc = 4.5 to 5.5 v) note: 1. this is preliminary data. table 6a. ac characteristics note: 1. for a restart condition, or following a write cycle. 2. sampled only, not 100% tested. 3. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. 4. this is preliminary data. symbol parameter test condition min. max. unit i li input leakage current (scl, sda) 0v v in v cc 2 a i lo output leakage current 0 v v out v cc, sda in hi-z 2 a i cc supply current v cc =5v, f c =400khz (rise/fall time < 30ns) 3ma i cc1 supply current (stand-by) v in = v ss or v cc , v cc = 5 v 5 a v il input low voltage (e0, e1, e2, scl, sda) C 0.3 0.3 v cc v v ih input high voltage (e0, e1, e2, scl, sda) 0.7v cc v cc +1 v v il input low voltage (wc ) C 0.3 0.5 v v ih input high voltage (wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 3 ma, v cc = 5 v 0.4 v symbol alt. parameter m24c16, m24c08, m24c04, m24c02, m24c01 unit v cc =4.5 to 5.5 v t a =0 to 70c or C40 to 85c v cc =2.5 to 5.5 v t a =0 to 70c or C40 to 85c v cc =1.8 to 3.6 v t a =0 to 70c or C40 to 85c 4 min max min max min max t ch1ch2 t r clock rise time 300 300 300 ns t cl1cl2 t f clock fall time 300 300 300 ns t dh1dh2 2 t r sda rise time 20 300 20 300 20 300 ns t dl1dl2 2 t f sda fall time 20 300 20 300 20 300 ns t chdx 1 t su:sta clock high to input transition 600 600 600 ns t chcl t high clock pulse width high 600 600 600 ns t dlcl t hd:sta input low to clock low (start) 600 600 600 ns t cldx t hd:dat clock low to input transition 0 0 0 s t clch t low clock pulse width low 1.3 1.3 1.3 s t dxcx t su:dat input transition to clock transition 100 100 100 ns t chdh t su:sto clock high to input high (stop) 600 600 600 ns t dhdl t buf input high to input low (bus free) 1.3 1.3 1.3 s t clqv 3 t aa clock low to data out valid 200 900 200 900 200 900 ns t clqx t dh data out hold time after clock low 200 200 200 ns f c f scl clock frequency 400 400 400 khz t w t wr write time 5 10 10 ms
m24c16, m24c08, m24c04, m24c02, m24c01 12/20 table 6b. ac characteristics 4 note: 1. for a restart condition, or following a write cycle. 2. sampled only, not 100% tested. 3. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. 4. this is preliminary data. symbol alt. parameter m24c16, m24c08, m24c04, m24c02, m24c01 unit v cc =4.5 to 5.5 v; t a =C40 to 125c min max t ch1ch2 t r clock rise time 300 ns t cl1cl2 t f clock fall time 300 ns t dh1dh2 2 t r sda rise time 20 300 ns t dl1dl2 2 t f sda fall time 20 300 ns t chdx 1 t su:sta clock high to input transition 600 ns t chcl t high clock pulse width high 600 ns t dlcl t hd:sta input low to clock low (start) 600 ns t cldx t hd:dat clock low to input transition 0 s t clch t low clock pulse width low 1.3 s t dxcx t su:dat input transition to clock transition 100 ns t chdh t su:sto clock high to input high (stop) 600 ns t dhdl t buf input high to input low (bus free) 1.3 s t clqv 3 t aa clock low to data out valid 200 900 ns t clqx t dh data out hold time after clock low 200 ns f c f scl clock frequency 400 khz t w t wr write time 10 ms table 7. ac measurement conditions input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc input and output timing reference voltages 0.3v cc to 0.7v cc figure 9. ac testing input output waveforms ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc table 8. input parameters 1 (t a = 25 c, f = 400 khz) note: 1. sampled only, not 100% tested. symbol parameter test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z wcl wc input impedance v in < 0.5 v 5 70 k w z wch wc input impedance v in > 0.7v cc 500 k w t ns pulse width ignored (input filter on scl and sda) single glitch 100 ns
13/20 m24c16, m24c08, m24c04, m24c02, m24c01 figure 10. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop & bus free data valid tclqv tclqx data output tchdh stop condition tchdx start condition write cycle tw ai00795b
m24c16, m24c08, m24c04, m24c02, m24c01 14/20 table 9. ordering information scheme note: 1. temperature range 1 available only on request. 2. sbga5 package available only for the m24c16-r ea 6 t example: m24c08 Cwdw1t memory capacity option 16 16 kbit (2048 x 8) t tape and reel packing 08 8 kbit (1024 x 8) 04 4 kbit (512 x 8) temperature range 02 2 kbit (256 x 8) 1 1 0 c to 70 c 01 1 kbit (128 x 8) 6 C40 c to 85 c 3 C40 c to 125 c operating voltage package blank 4.5 v to 5.5 v bn psdip8 (0.25 mm frame) w 2.5 v to 5.5 v mn so8 (150 mil width) r 1.8 v to 3.6 v dw tssop8 (169 mil width) ea sbga5 2 ordering information devices are shipped from the factory with the memory content set at all 1s (ffh). the notation used for the device number is as shown in table 9. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office.
15/20 m24c16, m24c08, m24c04, m24c02, m24c01 figure 11. psdip8 (bn) note: 1. drawing is not to scale. psdip-a a2 a1 a l e1 d e1 e n 1 c ea eb b1 b table 10. psdip8 - 8 pin plastic skinny dip, 0.25mm lead frame symb. mm inches typ. min. max. typ. min. max. a 3.90 5.90 0.154 0.232 a1 0.49 C 0.019 C a2 3.30 5.30 0.130 0.209 b 0.36 0.56 0.014 0.022 b1 1.15 1.65 0.045 0.065 c 0.20 0.36 0.008 0.014 d 9.20 9.90 0.362 0.390 e 7.62 C C 0.300 C C e1 6.00 6.70 0.236 0.264 e1 2.54 C C 0.100 C C ea 7.80 C 0.307 C eb 10.00 0.394 l 3.00 3.80 0.118 0.150 n8 8
m24c16, m24c08, m24c04, m24c02, m24c01 16/20 table 11. so8 - 8 lead plastic small outline, 150 mils body width symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 C C 0.050 C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004 figure 12. so8 narrow (mn) note: 1. drawing is not to scale. so-a e n cp b e a d c l a1 a 1 h h x 45?
17/20 m24c16, m24c08, m24c04, m24c02, m24c01 table 12. tssop8 - 8 lead thin shrink small outline symb. mm inches typ. min. max. typ. min. max. a 1.10 0.043 a1 0.05 0.15 0.002 0.006 a2 0.85 0.95 0.033 0.037 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 d 2.90 3.10 0.114 0.122 e 6.25 6.50 0.246 0.256 e1 4.30 4.50 0.169 0.177 e 0.65 C C 0.026 C C l 0.50 0.70 0.020 0.028 a 0 8 0 8 n8 8 cp 0.08 0.003 figure 13. tssop8 (dw) note: 1. drawing is not to scale. tssop 1 n cp n/2 die c l a1 e e1 d a2 a a e b
m24c16, m24c08, m24c04, m24c02, m24c01 18/20 figure 14. sbga5 (ea) C underside view (ball side) note: 1. drawing is not to scale. e1 a sbga-00 a1 d d1 e1 e e ball "1" table 13. sbga5 - 5 ball shell ball grid array symb. mm inches typ. min. max. typ. min. max. a 0.430 0.380 0.480 0.017 0.015 0.019 a1 0.180 0.150 0.210 0.007 0.006 0.008 d 1.900 1.870 1.930 0.075 0.074 0.076 d1 1.190 1.160 1.220 0.047 0.046 0.048 e 1.750 1.720 1.780 0.069 0.068 0.070 e1 1.070 1.040 1.100 0.042 0.041 0.043 e 0.800 0.770 0.830 0.031 0.030 0.033 ball diameter 0.350 0.320 0.380 0.014 0.013 0.015 n5 5
19/20 m24c16, m24c08, m24c04, m24c02, m24c01 table 14. revision history date description of revision 10-dec-1999 tssop8 turned-die package removed (p 2 and order information) lead temperature added for tssop8 in table 2 18-apr-2000 labelling change to fig-2d, correction of values for e and main caption for tab-13 05-may-2000 extra labelling to fig-2d
m24c16, m24c08, m24c04, m24c02, m24c01 20/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sing apore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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